1. Technical Field
The present invention relates generally to semiconductor devices and more particularly to a device including an NFET/PFET having dual etch stop liners and a protective layer for preventing the etching of an underlying silicide layer during removal of a portion of an etch stop liner.
2. Related Art
The application of stresses to field effect transistors (FETs) is known to improve their performance. When applied in a longitudinal direction (i.e., in the direction of current flow), tensile stress is known to enhance electron mobility (or n-channel FET (NFET) drive currents) while compressive stress is known to enhance hole mobility (or p-channel FET (PFET) drive currents).
One way to apply such stresses to a FET is the use of intrinsically-stressed barrier silicon nitride liners. For example, a tensile-stressed silicon nitride liner may be used to cause tension in an NFET channel while a compressively-stressed silicon nitride liner may be used to cause compression in a PFET channel. Accordingly, a dual/hybrid liner scheme is necessary to induce the desired stresses in an adjacent NFET and PFET.
In the formation of a dual/hybrid barrier nitride liner for stress enhancement of NFET/PFET devices, the first deposited liner must be removed in one of the two FET regions by patterning and etching. In order to ensure sufficient contact of a second deposited liner, it is preferable that the first liner be completely removed from the FET region. However, complete removal of the first liner requires an overetch, necessarily resulting in some etching of the underlying silicide. Etching of the silicide, in turn, results in an increase in silicide resistance (Rs).
FIG. 1 shows a device 100 typical of the prior art, comprising a buried silicon dioxide (BOX) 110, a shallow trench isolation (STI) 120, an n-channel field effect transistor (NFET) 140, a spacer 142, a p-channel field effect transistor (PFET) 150, a spacer 152, a tensile silicon nitride liner 170 adjacent NFET 140, a compressive silicon nitride liner 180 adjacent PFET 150, an intact silicide layer 130a, 130b, and an etched silicide layer 132a, 132b. As can be seen in FIG. 1, during the manufacture of device 100, the etching of tensile silicon nitride liner 170 from an area adjacent PFET 150 has resulted in etched silicide layer 132a, 132b being thinner than silicide layer 130a, 130b adjacent NFET 140. As noted above, etched silicide layer 132a, 132b has an increased Rs relative to silicide layer 130a, 130b. 
Silicide layer 130a, 130b normally has a thickness between about 15 nm and about 50 nm, with a corresponding Rs between about 6 ohm/sq and about 20 ohm/sq. By comparison, etched silicide layer 132a, 132b could have a thickness between about 5 nm and about 40 nm, with a corresponding Rs between about 12 ohm/sq and about 40 ohm/sq.
For technologies beyond 90 nm, which utilize sub-50 nm gate lengths and less than 100 nm diffusion widths, increases in Rs are unacceptable for at least two reasons. First, the increases in Rs will impact performance of the device. Second, erosion of the silicide layer increases the chance of failure by causing polysilicon conductor (PC) discontinuities in critical circuits.
Accordingly, a need exists for a semiconductor device having dual etch stop liners and an unetched silicide layer and methods for the manufacture of such a device.